24th IEEE Real Time Conference - ICISE, Quy Nhon, Vietnam (2025)

The preliminary beam test of the CYCIAE-230 cyclotron and its beam transportation system to the isocenter of the gantry was successfully conducted at the end of December 2023. During this, various beam transportation tests with different energies are carried out to verify the design of the energy selection system. The ESS consists of a pair of carbon wedge shape degraders, an apochromatic magnet system, and a related beam shape, the moment selecting slits. Once a beam energy is selected, the rest of the beam transportation system is controlled to follow the ESS, including synchronization of the 51 beamline magnets in total. The CYCIAE230 superconducting cyclotron extracts a fixed energy beam of 242.25MeV. The double wedge degrader and the beamline system are capable of modulating and transporting the beam with energy in a range of 242.25 MeV to 71.84 MeV. In energy range from 232.12 MeV to 71.84 MeV, it experimentally verified to be capable of switching down an energy layer (2mm water depth equivalent) within 50 milliseconds. Different from other degrader designs, the CIAE degrader has a large moment of Inertia, which makes it difficult to achieve fast control. A dedicated energy selection control system has been developed by CIAE, using the VxWorks real-time operating system and its multi-task scheduling to achieve fast control of the degrader and synchronization of the related magnets. To facilitate the commissioning of the beamline, an interpolation algorithm is also included in the reported control system, to automatically calculate the setpoints for different beam energy.

Speaker: Qiqi Song

A dedicated pencil beam scan system is developed and integrated into the proton therapy system of China Institute by a joint effort of Pyramid Consult Inc. and China Institute of Atomic Energy. In nozzle commissioning, a proton beam with an intensity of tens nA is provided by the CIAE beam production system, including a 242MeV superconducting cyclotron and a fast energy variable beam transportation system. Most of the scanning devices are commercial products from the pyramid, including the ion chambers, the helium beam path, the magnet, and its amplifier. A Scintillator - camera system named Lynx from IBA, is used to provide position readouts of the beam spot in the commissioning. A dedicated controlling software and related strategy for the beam commission of the scanning system is developed by the CIAE team. In the commissioning, firstly, a straightforward irradiation consisting of 114 beam spots is carried out to evaluate both the nonlinearity and cross-talks of the scanning magnets. Afterward, these coordinates are generated by Lynx and analyzed by the reported software. A modified 2D polynomial fitting, including Hyperbolic Functions, is invested in the commissioning to yield an open loop control accuracy in orders of millimeters. An iterative learning algorithm is also developed to give an even better accuracy. A 50mm separation irradiation map consisting of 37 points is carried out by combining these two corrections on the first day of commission, reaching an accuracy of 0.55mm. An irradiation field of 250mmX250mm is also verified at the same time.

Speaker: Xiong Rui

Due to various wireline transmission scenarios in different detector front-end readout environments, the high-speed chip-to-chip or board-to-board serial data transmission is encountering severe and various signal quality degredations. A general-purpose and high-speed transmitter (Tx) technique with tunable pre-emphasis function is crucial and in great demand. This paper presents the design and test results of a 10 Gb/s high-speed serial link transmitter with the adjustable 4-tap feedforward (FFE) function fabricated in a 55 nm CMOS technology.
The proposed FFE transmitter consists of a demultiplexer (DMUX), two latch-chains, four high-speed MUXes and an output combiner. With this half-rate topology, the needed maximum clock rate is 5 GHz, and thus the full CMOS logic cells can be safely used in the whole design to save power consumption. Besides, a custom-designed high-speed TSPC latch is designed to gain better performance in 5 Gb/s data rate. A high-speed CML-based 2:1 MUX is proposed to achieve the highest data combination in the system. The clock distribution tree is also deliberately designed between each sub-module to ensure suffice timing margins for latches, DMUX and MUXes over different PVT combinations.
The proposed 10 Gb/s 4-tap FFE transmitter features an area of 120 μm×290 μm, and the power consumption is around 50 mW including the CML output driver when working at the date rate of 10 Gbps. The chip has been designed and taped out, and will be tested in September 2023. The test results will be presented and discussed in the meeting.

Speaker: Qunqi Shi

This paper presents the design and test results of a 2.56Gbps deserializer with a full-rate clock and data recovery (CDR) fabricated in a 55nm CMOS process for applications in high-energy physics experiments.The PLL-based CDR recovers the 2.56GHz clock from the input data and retiming the data.Then the 2.56Gbps retimed data and the 2.56GHz recovered clock are used as the input for the deserializer.The 1:16 deserializer mainly includes a 1:4DEMUX module and a 4:16DEMUX module consisting of 1:4DEMUX units and two divider-by-4, which completes the conversion from a 2.56Gbps serial data to 16 channels 160 Mbps/Ch parallel data.The 1:4DEMUX unit in deserializer is implemented by orthogonal clock sampling, which reduces the requirement of clock frequency and increases the sampling margin.And the LC-VCO in CDR uses a capacitor array with high Q value to realize frequency fine tuning and optimize phase noise.The 2.56Gbps deserializer and the full-rate CDR are integrated in a large chip that has been taped out and fully tested. The test results show that the RMS jitter of the 2.56GHz recovered clock from CDR is 859.71fs with a phase noise of -110dB@1MHz. The total jitter (TJ) of the retimed 2.56Gbps data, which is output from the chip by a CML driver for test, is 32.54ps. And all the 16-channel outputs of the deserializer have been captured, saved and analyzed. Wide-open eyes have been captured, and the logic of 16-channel outputs of the deserializer has been verified. The detailed design and the test results will be presented in the paper.

Speakers: Prof. Di Guo (Central China Normal University), Qiangjun Chen

This paper presents the design and the test results of a 25 Gbps VCSEL driving ASIC fabricated in a 55 nm CMOS technology for detector front-end readout. This VCSEL driving ASIC is composed of an input equalizer stage, a pre-driver stage and a novel output driver stage. The input equalizer stage adopts a 5-step CTLE structure to compensate the high frequency loss at the PCB traces, bonding wires and input pads. It can boost maximum up to 5.8 dB at 18 GHz while providing a DC gain of 10.7 dB. To meet both the gain/bandwidth requirements and the area restriction, the pre-driver stage adopts the inductor-shared peaking technology and the active feedback structure. The total gain and the overall bandwidth of the pre-driver stage are better than 18 dB and 19.5 GHz at all process corners, respectively. The proposed output driver stage uses the double feedforward capacitor compensation, T-coil technique and the adjustable FFE pre-emphasis technique to improve the bandwidth. This VCSEL driving ASIC has been integrated in a customized optical module with a VCSEL array. Both the electrical function and the optical performance have been fully evaluated. The output optical eye diagram has passed the eye mask test at the data rate of 25 Gbps. The peak-to-peak jitter of 25 Gbps optical eye is 21.7 ps and the RMS jitter is 3.3 ps.

Speakers: Cong Zhao, Prof. Di Guo (Central China Normal University)

In this paper, a 4×6.25 Gbps serial link transmitter core has been designed for high-speed front-end ASICs. The transmitter core is implemented in a commercial 0.18 um CMOS technology. The core consists of a common PLL and four individual transmitter channels. Each channel contains a 2-stage 20:2 serializer, a 2-stage half-rate feed-forward equalizer and a clock manager circuit. A new architecture of the clock and data path is proposed, and the overall power consumption is reduced by 40% compared with previous works. At a data rate of 6.25 Gbps, the simulation results show that the PLL and transmitter feature a phase jitter of 1.3 ps RMS and 11.2 ps pk-pk respectively. The 4-channel transmitter core occupies 0.44 mm2 and dissipates 27.7 mW/Gbps from 1.8 V supply. The chip is being packaged and will be tested soon in December.

Speaker: Jiacheng Guo (University of Science and Technology of China (CN))

Abstract—A Compact front-end electronics (Compact_FEC) for reading Micromegas detector is presented in this paper. It includes the detector signal readout module, data acquisition module, and power supply module. The detector signal readout module uses a current-based readout chip, ADAS1128, which integrates 128 current amplifiers for multi-channel charge information measurement. After noise test and calibration, this readout electronics was applied to readout the Micromegas detectors. X-ray with iron-55 source and cosmic ray muon tracking tests were performed to test the energy-resolved and position-resolved performance. 5.9keV X-ray test results show that the Micromegas detector has the full peak charge of 391.3 fc at 5.9 KeV-X-rays, with an energy resolution of 19.50%(FWHM). The Ar escape peak charge of 183.7 fc, with the total peak charge to escape peak ratio of 2.13:1. 5.9keV X-ray measurements are in accordance with the theoretical values. The muon tracking test results for the detector X-dimension spatial resolution of 0.240 mm, Y-dimension spatial resolution of 0.243 mm. The results of the test show that the readout electronics can measure the track of the cosmic ray muon. In summary, the front-end electronics (Compact_FEC), in single-particle measurement mode, can measure signals from the Micromegas detector.
Index Terms — Current amplifiers, Micromegas detector, Readout electronics

Speaker: Ting Wang (University of Science and Technology of China)

The Hefei Advanced Light Facility (HALF) is the fourth-generation synchrotron radiation light source under construction. The linear accelerator system in HALF will accelerate the beam to 2.2GeV to reach the required luminosity, and a low-level radio frequency (LLRF) system should be adopted to achieve a high-phase-stability RF field inside the accelerator cavities. The phase stability required for the LLRF system is better than 0.02°RMS, which is necessary to achieve high precision phase measurement inside the LLRF system. In this paper, we introduce a phase-tracking-based digital LLRF system designed for the HALF linear accelerator system. The front-end module in this LLRF system is based on high-precision phase discriminator (PD) to obtain DC signal containing the phase information of input sinusoidal waveform. Besides, a differential amplifier and a digital-to-analog converter (DAC) is applied for tracking and amplifying of the phase changes, which is in order to match the input amplitude range of the backend analog-to-digital converter (ADC), and to increase the effective number of bits (ENOB) as much as possible. A Field Programmable Gate Array (FPGA) is adopted to calculate and extract phase information and control the phase-tracking DAC. At the end, we present the test results of the LLRF system and conduct further evaluation based on actual application scenarios in the HALF linear accelerator system.

Speaker: Zhenyan Li

Silicon photomultipliers (SiPMs) are widely recognized for their exceptional light response and high gain characteristics. Nonetheless, their practicality in fast timing applications is often impeded by their substantial terminal capacitance, which commonly exceeds 300 pF. To address this challenge, this study introduces a novel front-end readout electronics design. This architecture comprises a two-stage common-base transimpedance preamplifier and a 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analog-to-digital-converter (ADC). Through extensive SPICE simulations, utilizing the Hamamatsu S13360-6025 as the input source, the preamplifier circuit achieves a rise time of 700 ps and exhibits exceptional linearity. Meanwhile, experimental results from laser testing showcase that the proposed fast preamplifier design achieves a remarkable single-channel time resolution performance of better than 20 ps. As for the ADC circuit, considering the TSMC65nmLP process capability, a two-stage pipelined SAR structure is adopted, incorporating a two-step conversion technique (6-bit + 7-bit), with the second step employing redundancy design to reduce Vref buffer requirements. Experimental testing conducted at a sampling rate of 160M and an input condition of 80M reveals that, for Vpk = -1dBFS, the FFT spectrum analysis of the ADC demonstrates an effective number of bits (ENOB) of 9.34 and a spurious-free dynamic range (SFDR) of 73.8 dBc. Ongoing experiments are being systematically conducted, involving the connection of the fast preamplifier with the ADC, while future research endeavors encompass comprehensive investigations incorporating detectors to evaluate timing resolution in a holistic manner.

Speaker: Mr Xinchi Ran (Tsinghua University)

With the progress of material science and thin film preparation technology, the Transition-Edge Sensor (TES) detector-related technologies have been rapidly developed. The TES detector arrays find extensive applications in high-energy physics and nuclear radiation detection. The Frequency Division Multiplexing (FDM) technology is one of the mainstream multiplexing technologies used in TES readout that reduces thermal load. This paper presents the principle of the TES for applications in astrophysics and particle physics. Then, it proposes a room-temperature electronics readout scheme for the FDM readout system of the TES arrays. This scheme enables precise adjustment of the 40-channel TES bias signals so that the TES arrays can operate at the set optimal operating frequency. This scheme achieves high-precision amplification, sampling, processing, and feedback of TES signals. In the feedback algorithm, the logic resources of FPGA are used to achieve accurate phase compensation.

Speaker: Jianguo Liu (University of Science and Technology of China (CN))

Serial links are widely used for data transfer in Data Acquisition (DAQ) Systems of High Energy Physics (HEP) experiments. Pseudo-Random Binary Sequences (PRBS) has seen wide application in high-speed serial wireline communication systems as test patterns for link characterization and testing. A flexible architecture for FPGA-based PRBS generators is proposed, with a focus on high throughput and full reconfigurability. In order to meet the demands of increasing data rates, the proposed architecture employs a parallel datapath with high scalability. The architecture is designed to be fully parametric and reconfigurable, which allows dynamic reconfiguration of all parameters of the PRBS generator on the fly, including polynomial, seed and output width. Reconfiguration of the parameters is achieved by simply writing to corresponding registers, without the need to re-synthesize or re-configure the FPGA device. A built-in bootstrap logic is used to convert parameter register values to internal states that are fed to the datapath to generate the output bit sequence. The datapath is pipelined to facilitate optimized timing performance on FPGA devices. The proposed design can be utilized to characterize serial link performance under a great variety of different test patterns rather than several selected ones, providing broader insights. The architecture is implemented in CHISEL and verified on an Intel Agilex-7 FPGA and a 106.25-Gbps serial link, where results show promising performance and scalability.

Speaker: Chengyang Zhu (University of Science and Technology of China)

In the field of particle physics experiments, Time-of-Flight (ToF) is a powerful tool to perform particle identification, and the Time-to-Digital Converter (TDC) plays a crucial role in the high-precision time measurement. As the momentum of the particles to be studied increasingly goes high, the time resolution requirement becomes higher accordingly, and the TDC is expected to achieve picosecond (ps) time precision. Moreover, high-resolution measurements are also widely demanded in other scientific domains, such as LIDAR, TOF-PET, etc. In this work, the design and testing of a 16-channel coarse-fine hierarchical TDC is present. It utilizes a two-level conversion structure combined with a coarse counter to achieve a wide dynamic range with high time resolution. The coarse time is measured with a shared two-edge counting gray counter, and the fine time is obtained with a dedicated two-stage TDC, which is composed of a delay line TDC and a Vernier TDC. The bin size of TDC is approximate 7 ps. To implement a low-jitter clock generation circuit with a small area, a multiplying delay-locked loop was employed, and with a fixed patter noise calibration, the clock jitter was achieved better than 3 ps. The ASIC was implemented in a standard cost-effective 180 nm CMOS process, and test results show that the TDC reaches a dynamic range of 5 μs with 8.5 ps precision for all channels, while utilizing less than 10 mW/chn.

Speaker: Jiajun Qin (University of Science and Technology of China (CN))

To measure plasma density and provide real-time feedback for the control system, we have established a carbon dioxide dispersion interferometer (CO2-DI) system on the EAST tokamak device. Due to the low efficiency of the frequency-doubling crystal, the power of the second harmonic is extremely low. To obtain accurate interference information, it is necessary to use a lock-in amplifier to acquire modulation signals at 50k and 100k and process the intensity of this signal to obtain plasma density.
In our design, a lock-in amplifier module consists of two main components, the lock-in amplifier and the real-time data acquisition system. A dual-phase lock-in amplifier is designed. By two phase channels, the dual-phase lock-in amplifier can better handle complex signals and provide more comprehensive phase information. This capability makes it suitable for extraction of weak signals in CO2-DI. The real-time data processing system is implemented on a development board, utilizing Xilinx FPGA for digital signal processing and interfacing with the backend for output. The module is applied in CO2-DI to extract small signals and perform real-time data processing. We cross-validated the processed density data with results obtained from two other interferometers. The results indicate that the entire system has successfully obtained valid and verifiable electron density data.

Speaker: Yuan Yao (ASIPP, Chinese Academy Society)

In this article, a low-complexity maximum likelihood sequence equalizer (MLSE) algorithm for non-return-to-zero (NRZ) high-speed transceivers is proposed. In particle physics experiments and high-energy physics experiments, the amount of data transmission continues to increase, and transceivers play an important role. MLSE has received widespread attention because of its great advantages in eliminating inter-symbol interference (ISI), and it can work instead of a decision feedback equalizer (DFE). However, the complexity of MLSE also increases exponentially with the traceback length and equalizer order. Therefore, it is important to reduce the complexity of MLSE while ensuring its performance. This article simplifies the calculation of transition metrics for MLSE, eliminating the need for complex state calculations and result storage. A configurable and highly flexible transceiver simulation system is designed based on a field programmable gate array (FPGA), and the proposed algorithm is tested with this system. Quartus software synthesis results show that the proposed algorithm significantly reduces resource consumption without loss of algorithm performance.

Speaker: Dongwei Zou (University of Science and Technology of China)

CMOS pixel detectors, characterized by high spatial resolution, high sensitivity, and low material budget, are ideal for tracking charged particles. As a result, they have been widely used in particle physics experiments, and are considered the preferred technology for future vertex detectors. Particle physics experiments are constantly moving toward higher luminosities, placing greater demands on future detector performance. The integration of high-precision time measurement functions in CMOS pixel detectors allows the simultaneous measurement of particle hit positions and time of arrival (TOA). This so-called 4-D (four-dimensional) tracking capability allows for event discrimination on the time scale, reducing event pile-up and improving particle track reconstruction. To investigate the feasibility of integrating high-precision time measurement capabilities into CMOS pixel detectors, a pixel matrix prototype chip has been designed, based on a CIS 180 nm process. Each pixel in the pixel matrix is composed of a charge collection diode, a front-end charge signal processing circuit optimized for high timing accuracy, and a common time quantization circuit shared by 8 pixels. In response to the demand for low power consumption and high reliability in the pixel circuits, a time quantization method has been employed that combines fine time stamp measurements within the pixel and coarse time stamp measurements at the periphery of the pixel matrix. This method, along with a fully synchronous zero-suppression readout approach, achieves a time digitization of TOA with a bin size of 2 ns.

Speaker: Mr Boyu Cheng (University of Science and Technology of China)

Timepix is a semiconductor single-particle-counting pixel detector developed by the Medipix2 Collaboration at CERN. Timepix can create images of the traces of recored particles. Each arriving particle leaves a separate trail on the detector due to the charge sharing effect. The radiation trace on a image provides useful information for identifying the recorded paticles as well as their paths. The aim of this study is to propose a cluster classification algorithm for separating and analyzing each cluster inside an image. First, the clusters are extracted separately using the algorithm based on the definition of a cluster: a group of adjacent pixels that is independent of other clusters. Next, cluster's morphology parameters (number of inner/border pixels, width, height, cluster area radius, maximum distance in clusters, and so on) are examined. Finally, all clusters were divided into the following groups based on their geometrical features: dot, small blob, curly track, heavy blob, heavy track, and straight track. This study presents a quick and efficient framework for analyzing Timepix silicon detector data.

Speaker: Mr Trình Nguyễn Ngọc Quốc

Super Tau-Charm Facility (STCF) is one of the important options for accelerator-based particle physics in China. The operation of the STCF will provide a unique platform for the study of tau-charm physics and hadron physics.
Electromagnetic Calorimeter (ECAL) is one of the important sub-detectors of STCF, and Its core task is the precise measurement of photons. In the face of complex background environment, STCF ECAL needs to obtain accurate energy information and time information of photons at the same time to effectively suppress the background, so compared with traditional electromagnetic energy generators, STCF ECAL puts forward higher requirements for temporal resolution.
STCF ECAL selects pure Csium iodide (pCsI) as its scintillation crystal, and uses a large-area avalanche photodiode (APD) to make up for the shortcomings of low pCsI optical yield.
In order to meet the above readout electronics requirements, this paper determines the energy measurement scheme based on the Charge Sensitive Amplifier (CSA), and uses algorithm to deal with the pile-up signal, and the energy information and time information that meet the measurement requirements of STCF ECAL can be obtained.
In order to meet the needs of high-precision energy and time measurement in the environment of high case rate of STCF ECAL, the readout electronics scheme was studied and designed, and the feasibility of the scheme was verified by combining with the prototype electronics system, which provided a technical basis for the future development of STCF ECAL.

Speaker: Hanlin YU (University of Science and Technology of China)

Speakers: Helmand Shayan, Dr Markus Lange-Hegermann

The Belle II experiment seeks physics beyond the standard model of particle physics exploiting the data provided from the SuperKEKB accelerator.
To maximise the sensitivity to physics beyond the standard model, we collect as much data as possible.
Minimising the time without data-taking is a key to collect more data.
We have started our physics data-taking on March 2019, maintained the good data-taking efficiency since then.
Nevertheless, we encountered various problems and errors during our operation.
During the first running period (2019-2022), we established a system which automatically diagnose and fix known errors with no human interaction, hence we minimise the time without data-taking.
In the shutdown period (2022-2023), we implement a number of new alarms to monitor the detector environment, the data quality, and the data-acquisition system, thereby, we ensure the detector safety and the data quality in the next running period (2024-2027).
In the case of severe errors, it is expected that we encounter multiple alarms at the same time during the next running period.
In order to categorise the alarms activated simultaneously, we adopt the alarm system based on Control System Studio (Phoebus).
In this contribution, we present the current status of the system together with the difficulties experienced during the operation.

Speaker: Takuto Kunigo (KEK (IPNS))

Positron emission tomography (PET) is an advanced clinical examination imaging technology in the field of nuclear medicine. We will describe a novel PET module using a soft-core analog-to-digital converter (ADC) based on time-to-digital converter (TDC). The soft-core ADC is implemented in an FPGA. In the hardware design, the FPGA-based ADC (FPGA-ADC) only requires one resistor and an FPGA. FPGA-ADC allows users to program the sampling rate and adjust the dynamic range of the ADC with small modifications. This design is characterized by flexibility and high density, which can greatly reduce the size of readout circuits for the PET module.
In this PET module, detector will use a 15×15 (the size of crystal bar: 1.535 mm ×1.535mm ×20 mm) LYSO crystal array coupled with an 8×8 SiPM (J-series, from ON Semiconductor) array. The FPGA-ADC serves as the main part of the data acquisition (DAQ) system. For coincidence timing measurement, one reference detector is used in our experiment and to remove the background noise of LYSO crystal. It is possible for the FPGA-ADC to perform full waveform sampling on the raw signal of PET module. Good position and energy resolution can be achieved using the FPGA-ADC for the PET module.

Speaker: songqing liu

The Low Energy X-ray Polarization Detector (LPD) is one of the three payloads of the Gamma-ray Burst (GRB) Polarization Detector Space Station Detection Facility.LPD payload contains technologies such as the silicon pixel detector chip, the GMCP and high-power power supply. Pixel chip needs to be characterized by high effective detection area, high spatial resolution and low power consumption, which poses new challenges to performance requirements of the readout module of the chip.
This paper designs a pixel chip Topmetal-L with a novel readout scheme,the readout mode of the chip adopts the Region of interest (ROI) readout,it realizes fast readout for pixel units with particle injection. The ROI readout module is embedded in an L-shaped pattern around the pixel array, and module quickly reads out effective pixels by confirming the start pixel, the cutoff pixel, and number of pixels jump during scanning.The electronic system collects and processes the output signals of the pixel units, determines the areas where there is particle injection, and feeds back to the module to quickly scan to that pixel area and read it out. The module can control the driving circuit of each pixel, reducing chip power consumption.
The simulation results show that ROI readout effectively improves the readout rate of the chip and can meet the readout requirements under the strongest GRB conditions. The module can achieve fast readout with only one channel, significantly reducing the electronic power consumption of the payload. The introduction of drive switch effectively reduces the power consumption of the chip.

Speaker: Mr 强 周 (华中师范大学)

The super tau-charm facility(STCF) is a proposed e+e- collider producing a data sample 100 times higher than present tau-charm factory (BEPCII). The inner tracker of STCF should have certain position resolution, time resolution, charge measurement function and low power consumption and one of its alternative options is semiconductor detector based on monolithic active pixel sensor (MAPS). However existing readout structures of MAPS either have high power consumption or cannot readout ToT information correctly. To satisfy these requirements, a novel readout scheme has been developed in a full-custom manner. On the one side, it uses VCO in super pixels to record time-of-arrival (ToA) at 500MHz with extremely low static power consumption. On the other side, outputs of front-end circuits are combined through OR gates with the interval of multiple pixels in both directions, which avoids the loss of time-over-threshold (ToT) caused by OR gates. Finally, a group address is read out simultaneously to prevent degradation of position resolution caused by channels merging. A readout calculation model has been established based on MATLAB and simulation results illustrate the readout efficiency is higher than 99% until hit rate becomes 10 MHz/cm2, which corresponds to more than 10 times average counting rate of STCF ITK. According to simulation, the digital power consumption is lower than 30 mW/cm2 while timing resolution of ToA is 2 ns.

Speaker: Dongwei Xuan (University of Science and Technology of China)

Speaker: Mr Xuanzheng Yang

The peak luminosity of the Super Tau-Charm Facility (STCF) proposed by the Chinese particle physics community is about an order of magnitude greater than the present Tau-Charm factory. In the STCF, the micro-resistive well ($\mu$RWELL) based inner tracker detector, located closest to the beamline, demands a new high-rate, low-noise, and low power Application Specific Integrated Circuit (ASIC). The first version prototype ASIC integrates 32 readout channels, each consisting of a Charge Sensitive Amplifier (CSA), a Pole-Zero Cancellation (PZC), a shaper, and an output buffer. The supply voltage is designed to be 0.8 V to reduce power consumption while maintaining the same channel thermal noise and transconductance, and the core amplifier of the CSA achieves an open-loop gain of 74.2 dB and a Gain-BandWidth product (GBW) of 1.55 GHz with only 900 $\mu$W power consumption. In addition, a fast recovery circuit is designed to reduce the dead time. This ASIC has been taped out in a 0.18 $\mu$m CMOS process and a series of post-layout simulations have been performed. The dead time for a single channel is less than 250 ns, resulting in a maximum counting rate capability of 4 MHz. The equivalent noise charge (ENC) is 698 e + 23 e/pF while the power consumption is about 2.2 mW per channel, resulting in a figure of merit (FOM) of only 0.31 pJ.

Speaker: Mr Jiaming Li (University of Science and Technology of China)

Speaker: Weijia Han (Institute of Modern Physics, Chinese Academy of Sciences)

As the leading research platform of heavy-ion science in China, the heavy-ion physics and heavy-ion applications at the Heavy Ion Research Facility in Lanzhou (HIRFL) and the High-Intensity heavy-ion Accelerator Facility (HIAF) drive the development of new detector technology. A Monolithic Active Pixel Sensor (MAPS) has been designed in a 130nm process for HIRLF and HIAF. This MAPS can measure the energy deposition, the hit position, and the arrival time of the particle hit. As the critical component of this MAPS, a 14-bit 40MS/s regional pipeline ADC converts the analog energy and time signal from the pixels into digital data. It adopts the structure of SHA(sample-and-hold)-less and a first stage of 3.5-bit. Additionally, in order to improve the accuracy of conversion, bootstrapped switches, input offset storage technology, and the redundancy algorithm have been used in the design. With a power consumption of 138mW and an area of 1380μm×1300μm, this ADC can achieve the SFDR of 98.60dB, SINAD of 83.36dB, and ENOB of 13.56-bit.

Speaker: Yuan Tian

Since using X-ray pulsars for autonomous navigation of spacecraft was proposed, it has attracted attention from all parties because of its superior performance. As a commonly used semiconductor detector, the Silicon Drift Detector has high energy resolution, high linearity, and low noise, which are optimized for the detection of X-rays in the range of 0.5 keV to 10 keV.
The readout chip, fabricated in CMOS 130 nm, has 5 mm × 5 mm dimensions. The core of the IC is a matrix of 40×50 pixels with 80 um ×80 um pixel size. When SDD converts the incoming photons of X-ray into charge changes, the readout circuits will receive and convert these slight charges into a voltage proportional to the X-ray photon's energy. The chip uses the event-driven method to output the addresses of the pixels being hit and the corresponding energy signal of the incident X-ray photon and outputs the arrival time of the X-ray photon.
The power consumption is 31uW/pixel at a 1.5V power supply. The following simulation results use the default status of the chip after it is powered on as an example, and the readout electronics are optimized for collecting holes in this state. The charge to voltage gain of CSA is 96.13 μV/e- and the equivalent noise charge is equal to 36 e- rms (@detector self-capacitance Cdet=50fF). The pixel-to-pixel offset spread of the pixel matrix reached σ = 10.6 mV rms, and it was reduced to σ = 1.51 mV rms after correction by trim DAC.

Speaker: Mr Wenxuan Cao (Harbin Institute of Technology)

The traditional USB 3.0 communication based on FPGA uses an external chip as a USB PHY or a USB controller including a USB PHY. This paper realizes a USB 3.0 controller using FPGA resources, in which FPGA logic realizes a serial interface engine, and an FPGA internal transceiver is a USB PHY. Used slices percent after implementation is ~5% in Kintex-7 325t. The test result shows that the speed of USB 3.0 is more than 320 MB/s bulk-in and bulk-out transfers.

Speaker: Zhe Ning

In particle physics and nuclear physics experiments, especially experiments based on particle accelerators, the data transmission rate of the detector is very high. These high throughput data from the front-end electronic of the detector need to be transmitted to the PC for the selection and summary of the event. Data acquisition (DAQ) systems with high density, scalability, and easy upgrading are essential to simplify the reading architecture of the entire experiment. A common data acquisition unit (CDAU) has been designed in a scalable DAQ system for particle physics and nuclear physics experiments at the High Intensity Heavy Ion Accelerator Facility (HIAF). The CDAU is a PCIe-based FPGA data acquisition readout unit. The same unit handles the data acquisition and distributes slow control to the detector's front-end electronics. The CDAU is based on a PCI Express (PCIe) Gen 2 × 8 interface and interfaces to eight optical links via a QSFP transceiver and four SFP+ transceivers for data collection, packaging, and transmission, using a Xilinx Kintex series FPGA as its central chip, combined with optical interfaces and peripheral circuitry. This paper presents the design of the CDAU, its performance, and its application test. As a result, it is proved that the CDAU can perfectly realize data transfer through the transmission link and accomplish data restoration. Thus, the system can meet the needs of HIAF experiments. We are now preparing joint tests with different multi-channel detectors in physics experiments. More experimental results will be presented in the meeting.

Speakers: Chengcheng Liu (Institute of Modern Physics, Chinese Academy of Sciences), Mr Honglin Zhang (Institute of Modern Physics, Chinese Academy of Sciences), Prof. Haibo Yang (Institute of Modern Physics, Chinese Academy of Sciences), Mr Jieyu Zhu (Institute of Modern Physics, Chinese Academy of Sciences), Mr Xianqin Li (Institute of Modern Physics, Chinese Academy of Sciences), Prof. Chengxin Zhao (Institute of Modern Physics, CAS)

The Very Large Area gamma-ray Space Telescope (VLAST) is a high-energy detection satellite proposed by Chinese scientists aimed at conducting high-energy resolution spatial observations of gamma rays with unprecedented acceptance. As one of its sub-detectors, the High-Energy Imaging Calorimeter (HEIC) is used to measure the energy deposited by incident particles and to identify particles based on the shape differences between electromagnetic showers and hadronic showers. To achieve detection of 0.1 GeV-20 TeV gamma rays and electrons, a prototype calorimeter was proposed, which is composed of four layers, each with 25 BGO (Bismuth Germanate Oxide) crystal. Two identical Avalanche photodiodes (APD) are used for photoelectric conversion of a crystal, one of which is interposed with an attenuating filter. This paper proposes a readout electronics system for the prototype calorimeter. Signals from the APDs are amplified and shaped by CSA (Charge Sensitive Amplifier), then split into high and low electronics gains to achieve a large dynamic range. The analog signals are digitized by ADC (Analog-to-Digital Converter), and the waveform data of each layer is concentrated by Data Concentrator Module (DCM) and sent to computer for processing. The key indexes of energy linearity, noise level, and dynamic range were preliminarily studied. The ratio of the maximum input charge to equivalent noise charge in the readout electronics is about 1.4 × 10$^4$, which meets the large dynamic range requirements of the readout system.

Speaker: Qian Chen (University of Science and Technology of China (CN))

The High-Intensity heavy-ion Accelerator Facility (HIAF) is under construction to generate intense beams of primary and radioactive ions for various research fields. Among the different detector technologies, the Monolithic Active Pixel Sensor (MAPS) stands out due to its integration of the pixel matrix and readout circuit into a single silicon substrate. Hence, a MAPS named Nupix-A2 has been developed in a 130-nm High Resistivity CMOS process. The Nupix-A2 can simultaneously measure energy, arrival time, and position of the particle hits. What is more, the Nupix-A2 offers two operation modes, the full-readout mode and fast-readout mode, for different applications. It comprises a 128×128 pixel array, a digital-to-analog converter array, and a digital control module. The size of each pixel is 30 μm×30 μm. The Nupix-A2 can measure energy deposition from 300 e- to over 50 ke- and time duration from 13 μs to 140 μs. The S-cure shows the performance of the comparator, while the transfer noise (TN) is approximately 14.3258 e-, and the threshold is ∼300.112 e-. For the energy path, while using the test capacitor to inject charge, a maximum Integral Non-Linearity (INL) of 1.568% was observed within the 0 to 23.58 ke- range. As for the time path, when the range is 40 μs with the charging current at ∼4 nA, the maximum INL value is 2.88%. This paper will discuss the design and preliminary test of the Nupix-A2.

Speaker: Ju Huang (Institute of Modern Physics, Chinese Academy of Sciences)

The Transition Radiation Detector (TRD) of the High Energy Cosmic Radiation Detection facility (HERD) utilizes the relationship between high-energy charged particle transition radiation and the Lorentz factor to calibrate the energy of TeV-band protons in HERD calorimeters. It can also independently conduct X-ray observation and monitor Gamma-Ray Bursts . The TRD mainly consists of detector units, front-end electronics, and data acquisition system. The data acquisition system is responsible for the overall power management of the TRD, communication and triggering between the TRD and HERD, data processing of the detector units, control of multiple modules within the TRD, and in-orbit operation of the whole TRD. Here we report a prototype of the TRD data acquisition system, which connects six front-end circuit boards, six high-voltage circuit boards, a turntable device, HERD triggering subsystem, and HERD electronics. It adopts a structure with separate data and electrical components, with the power sections of the front-end electronics, high-voltage, turntable device, and data acquisition system designed as power circuit boards, and the FEE data transmission and telemetry, triggering, main control, storage, and communication designed as data circuit boards. We tested our data acquisition system prototype at the European Organization for Nuclear Research, and the results show that the system can meet the requirements of the TRD prototype in terms of power, communication, data processing, and overall control. We also demonstrate that the data acquisition system has been redundantly designed to enhance adaptability.

Speaker: Hui Wang (Central China Normal University)

In this article, we describe the development of an electronic circuit for measuring the pulse amplitude of scintillation detectors using an Arduino Mega2560pro (Embed). The amplified analog signals are fed into a peak detector circuit (Lew Counts and Mark Murphy, Analog Dialogue 24-2, 1990). In addition to this circuit, we have incorporated components such as opamp comparators, flip-flops, and analog switches to ensure accurate signal sampling through the Arduino. To test the system's performance, we used standard pulses with amplitudes ranging from 200mV to 3200mV generated by the RIGOL DG4062 pulse generator. The survey results show a full-scale non-linearity of less than 0.5%. Furthermore, we measured the energy spectrum of gamma rays emitted by various isotopes such as Ba-133, Na-22, Cs-137, and Co-60 using a NaI(Tl) detector (model 44-10) and counter (model 4612) manufactured by Ludlum Measurements, Inc , and our system. The results indicate that the Full Width at Half Maximum (FWHM%) at 81KeV is 15.46%, at 356KeV is 9.90%, at 511KeV is 8.57%, at 662KeV is 8.36%, at 1173KeV is 5.24%, and at 1332KeV is 6.15%. This is a simple and cost-effective design that can be used to construct gamma-ray spectroscopy devices for educational purposes.

Speaker: Ms Thi Minh Hien Nguyen (Centre For Applications of Nuclear Technique in Industry)

A superconducting cyclotron based proton therapy system has been developed at China Institute of Atomic Energy (CIAE) for years. The system has technical advantages such as high dose rate, fast energy varying, compact structure, and low energy consumption. From the cyclotron to the nozzle, the beam line employed 51 magnets, including six 30°, one 60°, and two 75° dipoles. It can be seen that its strict symmetry ensures the better beam optics, such as chromatic aberration for the beam with wide energy range. In order to meet the beam commissioning needs of such high-quality beam lines, the beam diagnostics system has been developed in house successfully. Along the beam line, the system includes: 1) 7 standardized comprehensive diagnostic units (a combination of Faraday cup, dual wires scanner, and optical beam profile monitor); 2) 4 pairs of X-Y slits for energy selection and emittance re-definition; 3) several separate circular collimators, fast beam cutoff devices, and online monitoring ionization chambers for beam position, as well as Faraday cup for measuring beam intensity in the air section for flexible use. In this paper, the design of the diagnostic system, the specialized electronics, the EMC consideration will be given. And the dual wire structure for pA level weak beam will be introduced, the Ce doped yttrium aluminum garnet (Ce:YAG), which is an important photonic material that is used as a yellow phosphor for white light emitting diodes, has very low intensity threshold for proton beam profile measurement will also presented in detail.

Speaker: Yang Wang

We have developed a digital waveform processing system with AMD RFSoC.
It is optimized system for experiments at RIKEN RI Beam Factory(RIBF) that is an accelerator facility in Japan.
This system is aimed at simultaneous measurement of TOF with high-resolution and ΔE using plastic scintillators.
The AMD RFSoC includes 4GHz FADC, FPGA, and CPU, and it is expected that this system that allows pipeline processing of high frequency signals without dead time can be established.
We have successfully developed the algorithm to obtained timing and charge information simultaneously by adopting centroid calculation for the waveform processing method. Especially, a very good timing resolution of 9 ps in sigma was achieved. At present, we are trying to implement this method to RFSoC as an FPGA IP core.
In this contribution, the algorithm for the extraction of timing and charge information from a waveform, and the implementation of FPGA firmware will be reported.

Speaker: Shoko Takeshige (Rikkyo University, RIKEN Nishina Center)

Superconducting transition-edge sensor (TES), operating in the mK temperature range, exhibit extremely low noise levels and excellent energy resolution. TES is widely used in the detection of cosmic microwave background radiation (CMB) and in synchrotron radiation, free-electron laser spectrometers. As the number of detector increases, the heat loading to the mK stage of refrigerator from the conducting of the read out cable from the mK stage to room-temperature will increase significantly. As the cooling capacity of refrigerator at mK is limited, this will limit the scale of the TES array. To increase the number of the TES detector, the mutiplexing cryogenic readout electronics is involed to readuce the number of the read out cable. The most mature technology is the time-division multiplexing (TDM) superconducting quantum interference device (SQUID). This paper focuses on the development of warm readout electronics for TDM. The two-stage SQUID readout architecture of TDM achieves multiplexed readout of multiple detectors by cyclically selecting each row’s first-stage SQUID, controlled by SQUID superconducting switching. This greatly reduces power consumption at each stage. We use a analog-to-digital converter (ADC) with a sampling rate of up to 125MSPS and 16-bit resolution to receive data. The data is then processed in real-time using a digital proportional-integral-derivative (PID) feedback algorithm in FPGA. We also use a 16-bit, 2.8GSPS digital-to-analog converter (DAC) to send synchronous SQUID magnetic flux locking signals. The goal of this work is to achieve a single-channel 20:1 multiplexing factor and to perform high-speed real-time data processing based on FPGA, GPU.

Speaker: Mr Nan Li (Shandong University)

The CSR External-target Experiment (CEE) at the Heavy Ion Research Facility at Lanzhou (HIRFL) will be the first large-scale experiment in nuclear physics independently developed in China, covering the GeV energy regime. As a major detector of CEE, The Zero Degree Calorimeter (ZDC) measures the centrality and reaction plane of the nuclear-nuclear collision from the hadron background. It comprises Plastic Scintillator (PS) crystal bars with a fan-shaped size for each. The PS bars directly coupled with a PMT (photomultiplier tube) to convert charged particles into electrical signals. The readout electronics consists of 12 Frond-End Cards (FECs), 12 Read Control Units (RCUs), one sub-trigger module, one sub-DAQ module, and one sub-clock module. In addition, there is one HV (High Voltage) crate providing a high voltage supply for the PMTs to provide power supply for the nearby PMTs. On the basis of the previous version of the prototype, in order to improve the performance of the detector, achieve a wider measurement range, and better electronic performance. This article introduces the upgrade of detector readout methods, electronic hardware and data processing algorithms, integration with CEE DAQ, trigger, clock and other subsystems, and long-term stable operation in engineering. The test results indicate that the noise performance is less than 1 mV (RMS), the nonlinearity of the full readout electronics is less than 0.7%. In addition, cosmic ray test results demonstrate that the readout electronics can reach good performance.

Speaker: Xianqin Li (Institute of modern physics, Chinese Academy of Sciences)

The High Energy Cosmic Radiation Detection Facility (HERD) is a part of the Chinese Cosmic Lighthouse Program in China’s Space Station, which will be launched in 2027. HERD is expected to work ten years in orbit and will indirectly detect dark matter, measure cosmic rays, and observe high-energy gamma rays. As a sub-detector of HERD, the transition radiation detector's (TRD) main scientific goal is to calibrate the electromagnetic Calorimeter (CALO) at the TeV energy range, improve the measurement accuracy of the CALO, and detect astronomical phenomena of high-energy gamma rays. The front-end readout electronic (FEE) of the prototype TRD uses four SAMPA ASICs for 128 anode signals, realizing a high-speed, low-power, and high-reliability data acquisition system. The FEE uses the R422 bus to communicate with back-end electronics for commands, state parameters, environmental parameters, and triggers. Scientific data transmission at 80 Mbps via LVDS protocol. The performance test results show that the dynamic range of the FEE is 0-100 fC, the RMSE of the channel noise is less than 1.7 fC, the linearity can reach 0.2%, and the amplitude resolution is better than 3% when the input charges exceed 20 fC. A beam test was performed at the CERN SPS and PS complex to verify the FEE performance further, and the experimental results show that the FEE meets the readout requirements of the prototype TRD and accurately obtains the energy spectrum of muons and electrons.

Speakers: Mr Jieyu Zhu (Institute of modern physics, Chinese Academy of Sciences), Mr Haibo Yang (Institute of modern physics, Chinese Academy of Sciences), Mr Yangzhou Su (Institute of modern physics, Chinese Academy of Sciences)

The next-generation muon spin spectrometers at the ISIS pulsed source, particularly ‘Super-MuSR,’ are poised to efficiently utilize the increased source intensity, achieving an impressive 1 G·event·hr-1 counting rate. This advancement hinges on the development of highly pixelated, high-density detector arrays covering a significant solid angle, each element fine-tuned for high-rate data acquisition.
Innovative strategies include full digitization of analog waveforms from SiPMs using digital signal processing (DSP), both at the software and firmware levels. This process is realized through the Xilinx Zynq® UltraScale+TM system on a chip, paired with 1 GHz sampling ADCs, leveraging event streaming technology and novel DSP data correction methods.
A critical enhancement is the digitizer's integration of a Kafka node in its firmware, enabling direct data transmission to the readout system and a ZeroMQ-based server for efficient slow control. These features underscore the system's seamless data processing and control capabilities.
Our discussion will explore this concept and its preliminary results, focusing on the prototype digitizing data acquisition system crucial for the 'digital data pipeline' (DDP). This advancement not only marks a technological milestone in detector design and data processing but also heralds new research avenues in muon spin spectroscopy.

Speaker: Francesco Caponio (Nuclear Instruments SRL)

Speakers: Mr Sean Cummings (Illinois Institute of Technology), Michael H L Wang

Abstract: The advancement of beam telescopes plays a pivotal role in propelling innovations in particle accelerators and refining detection systems. This research explores the architecture and performance attributes of the Hi’BT (Heavy-ion Beam Telescope) system, a pivotal tool for the forthcoming High-Intensity heavy-ion Accelerator Facility (HIAF) in China. At the heart of the Hi'BT design is the Topmetal-M sensor, which is able to achieve spatial accuracy in the micron range. Further empirical assessments are currently being conducted to corroborate the distinguished performance of the system.

Speaker: Dr Honglin Zhang (Institute of Modern Physics, CAS)

The COMET experiment at J-PARC aims to search for the neutrinoless transition of a muon to an electron ($\mu$-$e$ conversion). We have developed the readout electronics board called ROESTI for the COMET straw tube tracker. We plan to install the ROESTI near the detector, where the neutron fluence is expected on the order of $10^{12}$ neutron/cm$^2$. Neutron-induced single-event upsets disrupt the correct operation of the FPGA. We developed a novel hybrid scrubber of the Xilinx Soft Error Mitigation (SEM) and Xilinx soft microprocessor (Picoblaze) for the FPGA on the ROESTI.
The hybrid scrubber can correct both single-bit and multi-bit upsets in a frame, even without a reference memory that stores the original configuration data. Single-bit upsets are corrected by the SEM. When multi-bit upsets occur, the FPGA communicates with a DAQ PC via TCP/IP and receives the address of bit upsets. The bits at that address are inverted by the Picoblaze. As a result, the bits return to their original state and the multi-bit upsets are corrected.
The neutron irradiation tests were performed with the FPGA that implemented our hybrid scrubber. A total of 25 multi-bit upsets occurred, and all of them were corrected. This result indicates that the time required for FPGA firmware re-download can be reduced by around 76% compared to a conventional FPGA that implements the SEM only.
In this presentation, we will describe the implementation of the hybrid scrubber in the FPGA and the result of the neutron irradiation test.

Speaker: Eitaro Hamada

The report is dedicated to a measurement module of a dispersion interferometer for plasma density control at Globus-M2 tokamak (St. Petersburg, Russia). The system provides measuring of integral plasma density with resolution of 4·10^15 m^-2 every 20 μs. Such characteristics of the device allow using the results of its measurements in а feedback loops to real time plasma density control. The main elements of the measurement module are analog-to-digital converters and a digital data processing node based on SoC FPGA. The algorithm for plasma density calculating is implemented in the digital node. This algorithm bases on harmonic analysis of interferometer signals and it is resistant to noise and changes of modulation depth. The dispersion interferometer combined with the measurement module was installed at Globus-M2 in 2022. During the year operation, this system was proven to be reliable and robust diagnostic for line-integrated electron density measurements. The first experiments for controlling the electron density using dispersion interferometer as a detector were carried out at Globus-M2 in November 2023.

Speaker: Dr Svetlana Ivanenko (Budker Institute of Nuclear Physics SB RAS)

Speaker: Ran Chen (Central China Normal University)

In past decades, scientists have made many outstanding achievements in nuclear physics, nuclear astrophysics and atomic physics, biomedicine, and other fields based on accelerators. In order to promote the development of heavy ion accelerator technology and improve the research level, the next generation of the heavy ion research facility, HIAF, has been proposed. The beam energy of HIAF will reach GeV, and its operation is inseparable from the support of the beam monitoring system. The Nupix-H1, designed for the real time beam monitoring system in HIAF, has excellent position resolution and energy resolution and can simultaneously measure the energy and time information of the hit particles. Nupix-H1 includes a 64x64 pixel array, a pixel bias circuit, an analog buffer, and a digital scan readout circuit. Nupix-H1 can measure the deposition energy up to 5ke−, with ENC better than 15e− and INL better than 2.24%. The time measurement range is 22µs, and the maximum INL is 2.54%. In addition, we proposed an AC coupling method to increase charge collection efficiency.

Speaker: Hong Yuan (Institute of Modern Physics, CAS)

The Heavy Ion Research Facility in Lanzhou (HIRFL) and the High Intensity Heavy-ion Accelerator Facility (HIAF) are leading platforms for heavy ion scientific research in China. Based on them, the Electron-ion collider in China (EicC) is under construction to represent a new generation of physics experiments. These scientific facilities have led to the development of advanced detectors. Monolithic Active Pixel Sensor (MAPS) is a type of sensor with high spatial resolution, low noise, and low power consumption, and it is widely used in vertex and tracking detectors. A MAPS called Nupix-H2 designed in GSMC 130 nm quadra-well process can measure the particle hit's position, energy, and arrival time. This chip comprises a 128-row and 128-column pixel matrix with a pitch of 28.705 µm. Each pixel utilizes a Charge Sensitive Amplifier (CSA) structure to achieve energy measurement, coupled with a comparator and a shared counter for 16 pixels to achieve time measurement. With a novel automatic reset scheme of each pixel, the Nupix-H2 can work in a continuous mode. It achieves an Equivalent Noise Charge (ENC) of 21e- in the input range of 100 e- - 10 ke-, a maximum INL of 2% of the energy path output, and the conversion gain is approximately 55 µV/e-. With a 40 MHz clock used for the counter, the time resolution can reach close to 25 ns.

Speaker: Ms Rui He (Institute of Modern Physics, Chinese Academy of Sciences)

This study aims to optimize the energy resolution of the Topmetal-II pixel detector through the utilization of neural networks and curve-fitting strategies. The Topmetal-II plays a crucial role in capturing soft X-ray signals, enhancing its energy resolution is crucial for accurate measurements.
We employed neural networks, specifically Convolutional Neural Networks (CNNs), to train on the energy data of Topmetal-II, aiming to enhance its performance. Simultaneously, we employed curve-fitting techniques to model the response of Topmetal-II. Through the fitting of mathematical curves to the detector's energy response, our objective was to optimize its performance and improve energy resolution.
We employed a 12-bit ADC for the continuous acquisition of the energy channel of the Topmetal-II. The final statistical results indicate that adopting a neural network structure, with encoding and decoding layers each comprising 5 layers and 2 fully connected layers, along with the use of a Denoising AutoEncoder (DAE), yielded promising results. A comparison between DAE outputs and inputs showed a reduction in RMSE from 0.0447 to 0.0132, a decrease by a factor of 3.38, resulting in a 9.54% improvement in energy resolution. In curve fitting, the output function of the charge-sensitive amplifier was employed for data fitting. The RMSE decreased from 0.05385 to 0.01423, a reduction by a factor of 3.78, leading to an 11.1% enhancement in energy resolution. These results robustly support the progression of soft X-ray detection technology, indicating the potential for delivering more precise and reliable measurement outcomes in low-energy polarization detector (LPD) experiments.

Speaker: Ni Fang

In modern accelerator applications, stringent requirements are placed on the noise performance of digital converters. The noise from the digital converter will become part of the field noise seen by the beam, thus necessitating a low-noise, low-crosstalk digitizer. In response to this demand, this paper presents the design of a digital converter circuit board with 8 ADC channels and 2 DAC channels, which has been subjected to testing. The test results indicate that the circuit board possesses low noise and low crosstalk characteristics, rendering it suitable for reading accelerator signals.

Speaker: Mr Qiutong Pan (Tsinghua University)

Nuclear physics with radioactive beams has been the most dynamic frontier research field in nuclear science. The high intensity heavy-ion accelerator facility (HIAF) under construction is equipped with a high energy fragment separator (HFRS), characterized by high energy and high intensity. HFRS utilizes the Bρ-TOF-ΔE method for high magnetic rigidity, large ion-optical acceptance, and excellent particle identification, commonly used in nuclear fragmentation secondary beam devices. Among them, the energy loss detector ΔE is the key to particle identification. The energy loss detector is designed using the multiple sampling ionization chamber (MUSIC). It can significantly improve the energy resolution of the gas ionization chamber through multiple samplings. The readout electronics of the MUSIC consist of 16 charge sensitive preamplifiers (CSP) modules and two readout control electronics (RCE) modules. A single RCE has eight channels. The CSPs, placed inside the MUSIC, read out the MUSIC charge signals. The RCE receives the voltage pulses from the CSP, performs voltage signal amplification and filter, and digitizes the signal. The measured data is packed and transmitted to the DAQ system with a 10 Gb ethernet protocol. Comprehensive tests have been performed on the readout electronics. The test results indicate that the noise performance is less than 1.8 ADC values (RMS), and the nonlinearity of the full readout electronics is less than 0.17%. In addition, radiation source test results demonstrate that the readout electronics can reach good performance. We are preparing for beam experiments to further evaluate the performance of MUSIC and the electronics system.

Speakers: Dr Haibo Yang (Institute of Modern Physics, Chinese Academy of Sciences), Mr Xianqin Li (Institute of Modern Physics, Chinese Academy of Sciences), Prof. Chengxin Zhao (Institute of Modern Physics, CAS)

Silicon photomultiplier (SiPM) was increasingly applied in nuclear medicine imaging development in recent years, especially in positron emission tomography (PET) scanner. To achieve a cost-effective, power-efficient signal processing unit for the SiPM array, a compact 128-channel front-end electronic (FEE) system based on dual-polarity charge-to-digital converter (dQDC) was proposed. A dQTC circuit consists of two resistors, a commercial amplifier, an integration capacitor, a voltage-referenced receiver and a discharging I/O pin in the FPGA. The hardware of the 128-channel FEE consists of an analog board and an FPGA board. In the analog board, 128 channels of dQDC analog circuits are implemented. The FPGA board is based on a low-cost FPGA, instantiating 128 LVDS receivers that serve as 128 voltage comparators. The SSTLⅡ standard is used to maximize the dynamic range of the dQTC circuit. The electronics performance of the FEE is evaluated in terms of noise, linearity, and uniformity. A PET detector is used to verify the readout capability of the 128-channel FEE system. The PET detector is made up of a 15×15 lutetium-yttrium oxyorthosilicate (LYSO) array and two SiPMs. The LYSO array is coupled with the two SiPM array at two ends. With the 128-channel FEE, the energy resolution (ER) of the PET detector is about 13.2%, and Peak-to-Valley Ratio (PVR) is 6.02. Currently, a time-to-digital converter is being developed to achieve a high-precision timing measurement for the PET detector. All the results of the performance evaluations including electronics and detectors will be presented in the meeting.

Speaker: Bo Wang

A real time data acquisition system is being implemented using a configurable muti-functional FPGA PCIe card. The FPGA card acquires 16 channels signal at 250 kHz, calculates 512-point Fast Fourier Transform (FFT), and provides the full data set of both original raw data and FFT derived data to the real-time computer. Data is recorded to the Korea Superconducting Tokamak Advanced Research (KSTAR) MDSplus database outside of plasma control system (PCS) for analysis and internal to PCS for algorithm use. Part of the real time version of disruption event characterization and forecasting (DECAF) running inside PCS uses this input for internal calculations.
When constructing the FFT engine in hardware, Intel FFT IP core is used to implement FFT. The detailed pipelining and timing for 16 channel 512 sample points for the FFT engine is described in the paper. Dual FIFO and RAM ping pong architecture are used for data reading, processing, and writing. The test result shows that the pipelined FFT engine works as expected. This work was supported by DOE contract No. DEAC0209CH11466 and grant DE-SC0020415.

Speaker: Mr Weiguo Que (Princeton Plasma Physics Laboratory)

Intel AVX-512 is a Single Instruction Multiple Data (SIMD) instruction set based on x86 data center processors. Unlike traditional Single Instruction Single Data operations, a SIMD instruction can simultaneously execute operations on multiple data, effectively accelerating compute-intensive tasks. This feature is well-suited to the requirements of online data acquisition and processing in physical experiments. For example, during the data acquisition for pixel detectors, real-time image processing and optimization are essential to ensure image quality and accuracy. However, this process often demands substantial CPU computational resources within the system. By utilizing SIMD technology based on the AVX-512 extension instruction set to vectorize the code, the program's execution performance has been effectively improved, resulting in resource savings and enhanced system integration. Furthermore, this technology is applied to accelerating a software-based multiplicity trigger algorithm proposed in this paper, thereby achieving superior performance.
Key Words: AVX-512; SIMD; High Performance Computing; Image Processing; Software Triggering

Speaker: Mr Pengfei Xiao

The significance of the remote debugging capability cannot be overstated when it comes to separating the urgency of FPGA-based hardware deployment from the maturity of firmware design. Furthermore, the importance of sensor monitoring in the success of complex systems like TDAQ in high-energy physics experiments is evident, even though it presents fewer challenges compared to the TDAQ system itself. The integration and processing of data from diverse sensors remain a critical focus.
This research introduces an innovative solution known as the "Decoupler," specifically designed to address key challenges in FPGA-based systems, especially during the initial stages of firmware development and sensor monitoring.
The Decoupler utilizes an ESP32-based module with a slight modification to the JTAG connector pinout. It implements an xvc server for remote debugging and connects to an IOT-HUB for sensor data collection and control. This approach eliminates the need for additional hardware space and firmware resources. Notably, it simplifies integration and maximizes the utility of existing hardware. By leveraging the JTAG's Vref for power, the ESP32 module doesn't require an independent power supply and can operate in an ultra-low-power mode when debugging is unnecessary, conserving energy while still delivering near-real-time sensor data transmission.
Its ability to function independently of the FPGA's firmware development process and its utilization of existing JTAG connectors for both power and data transfer mark a significant advancement in the field.

Speaker: Yifan Yang (Universite Libre de Bruxelles (BE))

The article discusses a research presentation on the design and manufacture of handheld radiation measurement devices using Geiger-Muller tubes counting gamma radiation, applied in educational settings. The research and development aim to support educational training, aiding students in comprehending the interactions of radiation with matter, contributing to the dissemination of knowledge about atomic energy applications, and enhancing the quality of presentations at the Nuclear Research Institute Training Center. Initial results have led to the creation of a portable radiation measurement device utilizing Geiger-Muller tubes and a 10µCi Cs-137 gamma source, displaying the count on a 16×2 LCD screen, and powered by a 9VDC supply for ease of use and safety. This serves as a foundation for further research in developing radiation measurement devices using X-rays, with the goal of enhancing the visual and vivid aspects of lectures on atomic energy applications. The objective is to use gamma transmission methods without relying on complex and expensive equipment, ensuring radiation safety at the Training Center.

Speaker: Mr Dang Quoc Trieu (researcher)

The single crystal hot neutron diffractometer HEiDi is operated by Forschungszentrum Jülich at the research reactor FRM II in Garching. Core of the instrument is the 4-circle diffractometer, consisting of an Eulerian cradle for the sample and the detector arm. The detector of HEiDi is a single a 3He detector tube. In classical scans, in each step the axes of the 4-circle diffractometer are moved to the desired position and then the measurement is started. A reduction of measurement time can be achieved by measuring also during movement. The necessary synchronization between the motion subsystem and the detector is being implemented. The motion subsystem is based on a Siemens S7-1500 PLC and the synchronization uses its cam track technology objects.

Speaker: Harald Kleines

The Hyper-Kamiokande (Hyper-K) experiment is a next generation underground water Cherenkov detector designed to search for leptonic CP-violation and a wide science program, including neutrino astrophysics, and searches for nucleon decay.
The main photo-sensor used in the experiment is the 20" box-and-line R12860 PMT, an improved version of the ones used in Super-Kamiokande. Due to the tank size in Hyper-K, the electronics will be placed underwater to minimize the length of the photomultiplier cables. Because of this and the new PMT models, a new signal readout system had to be developed.
The requirements for this new digitizer are the possibility to set the trigger threshold to a 1/6 of p.e., a maximum signal rate of more than 1MHz (in case of supernova and electrons from decay of muons) and a power consumption of less than 1 W per channel.
The final design has 12 single channels made of discrete electronic components. Each channel has an input receiver that sends the signal into two different paths: one that creates a digital trigger and the other that goes to an integrator and then to two ADCs that measure the signal charge. To collect the data from the 12 channels the board is equipped with a Xilinx Kintex-7 FPGA, that will also measure the Time-over-Threshold and Time-of-Arrival.
The whole board mounts a switching power supply custom designed to generate all the voltages needed by the components present on the board.
The design is almost complete and will be finalized in 2024.

Speaker: Alessandro Di Nola (Universita Federico II e INFN Sezione di Napoli (IT))

For the upgrade of the High Intensity Proton Accelerator at PSI of injector cavities 2 and 4, a new digital radio frequency control system was developed using the IFC 1210 VME board. This system comprises three components: A single-board computer running the control system software and the real- time application, both running on a dual core P2020 PowerPC, as well as the FPGA Design utilizing a Virtex 6. The real-time application (RTAPP) covers three use cases: "Cavity Tuning”, “Startup FSM”, and “Calculate Statistics”. “Cavity Tuning” implements the controller for the cavity’s tuning system, which consists of two controllers. One controls the physical position of the two tuners within the cavity, and the other one provides the setpoint for the tuner controller and controls on the phase error between forward power and cavity pickup, ensuring minimum reflected power during operation. The “Startup FSM” governs the radio frequency control system during the startup procedure. Here, the cavity must overcome the multipactoring zone while minimizing reflected power and without overstressing the amplifiers. Finally, “Calculate Statistics” performs computations on measurement data from high resolution ADC RAW values, reducing the data load before forwarding them to the control system. The software design is split into four layers: Common, hardware, service and application layer. These layers cover 13 different components which are each assigned a dedicated thread. The update frequency of the components varies between 25 and 50Hz, real-time behavior is given if a deadline of 20ms or 40ms respectively can be guaranteed.

Speaker: Mario Jurcevic

The Heavy Ion Research Facility in Lanzhou (HIRFL) and the High Intensity Heavy-ion Accelerator Facility (HIAF) are advanced heavy-ion accelerators, which play a critical role in pursuing a deeper understanding of nuclear physics. The beam monitoring system, known as the eyes of the accelerators, is an essential part of the accelerator facilities. Its function is to monitor the beam parameters to improve the beam quality. The performance of the beam monitoring system determines the ability of researchers to enhance the quality of the beam. The Topmetal silicon pixel ASIC IMPix-S2 is a hybrid pixel readout ASIC independently developed by us. It can directly collect the space charge around the chip without interaction with particles, and is the core device of the beam current monitoring system. The IMPix-S2 was designed using a 0.13 μm process with an ASIC size of 23 mm × 2.24 mm for beam monitoring. The ASIC mainly consists of a sensitive area consisting of circuits such as pixel arrays and a non-sensitive area for readout control. The sensitive area has 16 banks of pixels, each bank has 28 rows × 48 columns of 29 um × 29 um pixels. Each pixel measures the energy of the collected charge by topmetal, CSA, peak-holding circuit and source follower circuits. The readout control adopts a rolling shutter scanning method, where each bank scans all its pixels simultaneously and sequentially to output the energy information off-chip.

Speaker: xiaoyang Niu

We implemented A LabVIEW-FPGA-Based Real-time processing system for Keda Torus eXperiment (KTX) as a part of Active Control Feedback Electronics System (ACFES). The processing system plays a role in real-time feedback control and communication between KTX central control system and hardware devices of ACFES.
Experiment results prove that the designed system provides a real-time data acquisition and feedback, offers convenient interact between CSS-Host-Slaves and can help ACFES hardware devices work perfectly, as a consequence, remarkably extends the discharge time of KTX.
We will briefly metion the hardware architecture and introduce the modularized software platfrm combined with the acquisition and aggregation FPGA logic.

Speaker: Jiahong Jiang (University of Science and Technology of China)

Many particle physics experiments utilize FPGAs in intense radiation environments, and they are concerned about SEUs. An SEU is a soft error that occurs when a charged particle plunges into the part of an SRAM or flip-flop that holds the data. Neutrons also have the possibility of causing SEUs because they can generate charged particles by interacting with atoms in semiconductor devices. We investigated SEUs particularly caused by thermal neutrons. The study employs a 28-nm CMOS FPGA from Xilinx Inc., implementing Soft Error Mitigation (SEM) Controller firmware to detect and correct SEUs. We performed a neutron irradiation test at the tandem accelerator to measure SEUs in various settings, including shielding with polyethylene blocks or ones containing Boron trioxide. To measure the fast- and thermal-neutron doses separately, we used a solid-state track detector CR39 (allyl diglycol carbonate). Results show successful reduction of fast neutrons in certain settings, affirming control measurements and we concluded thermal neutrons caused SEUs. In this presentation, we report details on the SEUs in FPGAs caused by thermal neutrons.

Speaker: Chihiro Yamada (Osaka University)

Speaker: Santosh Parajuli (Univ. Illinois at Urbana Champaign (US))